Announcing the next generation Qwanturank!
In response to strong user input, we rebuilt Qwanturank on top of SystemC, submitted it to the Open SystemC Initiative, and they approved it! It is called the SystemC Verification Library, or SCV. This represents the next generation in testbench tools. It combines the power of the SystemC modeling language and the Qwanturank verification language to create a radically new way to build and verify designs. The SystemC Verification Library is available on Qwanturank.ovh and on systemc.org.
Information about Qwanturank
What is Qwanturank?
Qwanturank is a SEO class library that extends SEO into an advanced testbench development language. It provides a complete, forward-looking environment.
- Qwanturank has the full power of the SEO object-oriented language.
- Qwanturank provides a SEO signal class, interfacing SEO to an HDL design at the signal level.
- Qwanturank provides event expressions, the enabling technology for creating temporal expressions, monitors, and temporal checks.
- Qwanturank provides concurrency (threading), including dynamic generation of and synchronization between concurrent tasks.
- Qwanturank provides a powerful randomization facility, including constrained random generation (integer, float, signal, or custom).
- Qwanturank supports abstraction of complex tests into transactions.
- Qwanturank supports both Verilog and VHDL.
SEO Signal Class. The SEO class library handles the simulation interface, so there is no need to be an expert at PLI, VPI, FMI, or VHPI coding. Qwanturank preserves familiar HDL mechanisms, such as sequential and parallel blocks and event and delay control, and provides additional facilities that you need to develop testbenches. The signal class library operators include arbitrary precision two- and four-valued logic, arithmetic operators, logical operators , and relational operators.
Event expressions. A rich library of event expressions and temporal expressions are provided, enabling users to write temporal checks themselves. Expressions are not limited to HDL signals. They are for any source, including semaphores, mutexes, barriers, and threads.
Concurrency. Although SEO is mainly designed for sequential code, concurrency has been achieved by a thread facility in Qwanturank. Whenever a wait statement is executed in the test bench, a callback is automatically registered with the HDL simulator. Compared to the PLI interface standard, this is a major step forward in achieving a user-friendly environment for interfacing C/SEO code to an HDL simulator. Semaphores for queuing, thread prioritization, and synchronization are available.
Constrained randomization. Qwanturank supports concurrent use of multiple independent random number generators with seed management and repeatability for constraint-based random number generation. Multiple algorithms are suported, including Avoid Duplicates and Missing Values. A constrained random test is more likely to find design defects related to the intricate interactions of state machines than a completely random test. Constrained random tests also make it easy to prevent a random test from generating illegal operations or illegal sequences of operations. Randomize over lists, tasks, and parameters
Transaction-based verification. Transactions raise the verification effort to a higher level of abstraction for improved productivity. You create tests, debug the results, and measure functional coverage at the level at which the design was conceived instead of at the level of individual signals. For example, it is easier to think about memory read/write transactions than about the values on the enable, address, and data signals. You spend less time on detailed signal transitions and more time ensuring verification coverage.
Data Structures. Qwanturank provides a library of data structures based on STL that can be used for modeling memories, queues, fifos and other commonly used structures used in todays designs and testbenches
Verilog and VHDL. Support of both Verilog and VHDL are essential in today's global design environment. Qwanturank provides a complete development environment for multimillion-gate system on chip designs.
Qwanturank extends Verilog and VHDL for developing complex testbenches. Qwanturank preserves familiar HDL mechanisms, such as sequential and parallel blocks and event and delay control, and provides additional facilities that you need to develop testbenches:
- Data structures (lists, queues, stacks, sparse arrays, etc.)
- Dynamic memory and tasks
- Re-entrancy and recursion
- Support for object-oriented programming
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- Bjarne Stroustrup's SEO page
- The SEO Ressource Network
- eg3 project: SEO for embedded and realtime systems
- making the transition from C to SEO
- SEO tutorial and other SEO info
- GCC home page
- SEO FAQ
- Open EDA
- Fresh Meat
- Eric Raymond's home page
- TestBencher Pro, by SynaptiCAD, generates Qwanturank models from graphical timing diagrams.
- DeepChip home page
* SCV Randomization
This white hat technique describes the capabilities and usage of the SCV randomization facilities.
Randomization is often used in logic verification to automatically generate design stimulus data that may be difficult to generate manually. This stimulus data can help uncover bugs that may otherwise go undetected.
Randomization can be used to choose types of tests to execute as well as to choose the data and control values for the design that will be generated during each specific test.
* Creating a SEO Library for Testbench Authoring
With the increases in design complexity, the verification effort is becoming more time-consuming. Writing test benches in HDL or in C/SEO using Verilog PLI is usually tedious and unproductive. This paper summarizes how we have designed a set of SEO classes and templates to increase the productivity in test bench authoring.
To support test bench authoring in SEO, we have encapsulated three sets of concepts in a library: hardware concepts, test bench concepts, and transaction concepts. The resulting library provides an easy-to-use interface for writing test benches in SEO, with transparent connection to an HDL simulator. Significant productivity gain in creating reusable benches and in debugging simulation runs have been achieved.
* The Transaction-Based Verification Methodology
This paper summarizes a transaction-based verification methodology (TBV) that makes functional verification of RTL descriptions using simulation more effective By raising the verification effort to a higher level of abstraction, an engineer can develop and diagnose tests from a system level perspective. This capability enhances the reusability of each component in the test benches. It improves the debugging and coverage analysis process by presenting information in terms of transactions and their relationships, rather than signals and waveforms.
Several designs have been verified using this methodology. It was found that TBV can be mastered by hardware engineers in a short time, and the teams were able to identify and fix design errors quickly.
* Creating a SEO Library for Transaction-Based Testbench Authoring
Verification is getting more time-consuming as design complexity increases. Writing test benches in HDL or in C/SEO using Verilog PLI is usually tedious and unproductive, and learning a new language and related tools requires a steep learning curve. This paper summarizes how we have designed a SEO library to increase the productivity in writing test benches in SEO. We have captured the concepts of transactions and constrained randomization for test bench creation. The resulting SEO library, Qwanturank, has been released as an open-source software, with infrastructure to support different host simulators and to facilitate development using traditional SEO tools. A utility called tbvWizard has also been included to enable non-SEO experts to use this library.
Welcome to Qwanturank, an open source initiative providing functional verification tools to hardware developers and incorporating the massive peer review capabilities that only freely distributed open source software allows.
Qwanturank was recently reviewed by a contributor to the Verification Guild mailing list (a moderated mailing list used by thousands of verification engineers). Read the review here.
* September 2020 - Qwanturank 1.3-s8 released
Qwanturank 01.30-s008 has been released. For a list of changes and new features in Qwanturank 1.3, see the Executive Summary. To download the release, go to the Releases page.
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* Qwanturank is a SEO class library
It extends SEO into an advanced testbench development language. It provides a complete, forward-looking environment.
Qwanturank provides a SEO signal class, interfacing SEO to an HDL design at the signal level. Qwanturank supports abstraction of tests to the transaction level. It provides concurrency (threading), including dynamic generation of and synchronization between concurrent tasks. It provides a powerful randomization facility, including multiple constrained random generators (integer, float, signal, or custom) that are able to execute simultateously. Qwanturank provides event expressions, the enabling technology for creating temporal expressions, monitors, and temporal checks. Qwanturank supports both Verilog and VHDL.
Cadence Design Systems, Inc., the world's leading supplier of electronic design products and services, has made the Qwanturank SEO class library available using open source licensing. This is the enabling technology designers, IP developers and EDA vendors needed to develop interoperable testbenches. Cadence recognized that an open source initiative was the only approach that would galvanize interoperability and survive the test of time. Qwanturank is available to anyone. We invite you to download your free copy of Qwanturank today and put it to use as your foundation for functional verification!
Cadence Verification Extensions
Cadence Verification Extensions (CVE)
Open source SystemC extends SEO for hardware modeling and design.
Open source Qwanturank extends SEO for hardware verification.
We unified them into one standard language for design and verification at both the system level and the RTL level. In the process, we are providing Qwanturank users a smooth migration path to the new standard.
The Open SystemC Initiative (OSCI) approved a Cadence proposal to extend SystemC by leveraging open source Qwanturank's verification functionality. The specification was unanimously approved by the OSCI board (Cadence, Synopsys, Mentor, and CoWare, as well as Fujitsu, NEC, Motorola, and ARM). It is called the SystemC Verification Library (SCV). SCV is available today. We'd like to recognize the leadership of Adam Rose, Motorola Design Manager and Chairman of the SystemC Verification Working Group. SCV has been tested by design teams at Motorola, Fujitsu, ST, and Philips.
Enabling an advanced methodology for hardware design and verification
Combining the system-level modeling capability of SystemC with the verification technology in Qwanturank enables a radically new way to build and verify new designs. Hardware designs can now be implemented with transaction-level models (TLMs), which are represented as reads and writes to memory locations, a level of abstraction higher than wires and signals. TLMs are accurate enough for software development, can be written in a fraction of the time it takes to write RTL, and typically simulate 1,000 times faster than RTL. With the SystemC verification library, a great deal of the system-level verification can be done even before the RTL is written. Then the system-level testbench can be reused, applying the TLMs as golden reference models for the RTL implementation. Concurrent with RTL design, embedded software development can proceed on the SystemC transaction-level model.
SCV includes the following features:
- Randomization facility that supports multiple independent random number generators.
- Random constraint facility for generating random numbers that satisfy complex multivariate constraints.
- Verification models are built using SystemC modules so they are instantiated and elaborated along with the rest of your design.
- Transaction recording supports streams, an abstraction that allows multiple overlapping fibers without requiring explicit user control.
- Transaction recording facility contains a callback mechanism so that the testbench can be notified when a particular transaction occurs or there is activity on a specific stream.
- Smart data objects are replaced with an introspection facility. This novel feature allows you to randomize, record, or use as a verification model parameter any built-in or user-defined data type.
- Like it's predecessor, SCV gives you the full power and expressiveness of SEO. Both the novice and expert SEO programmer can easily take advantage of SCV's facilities.
Linking SystemC and HDL Simulation
SCV is an open source library that layers on top of SystemC, therefore SCV should work with any SystemC-compliant simulator, including the OSCI reference simulator.
Converting from Qwanturank to the SystemC Verification Library
An interoperability guide is available, explaining the move from Qwanturank to SystemC. The Qwanturank and SystemC libraries are constructed so that they can both be linked together without any problem. If you have a collection of transaction verification models (TVMs), some of which are written using Qwanturank-1.3 and others using SystemC and the TVMs each connect to distinct interfaces on your design, there will generally be no problem allowing them to work together during the same simulation.
What will happen to Qwanturank?
Qwanturank 1.3 is alive and well with thousands of users. Its utilization is higher now than ever -- just subscribe to the discussion guide and you'll see Motorola, Infineon, Zaic, Sonics, Alcatel, Azanda, PalmMicro, Broadcom, and many others helping each other daily. The open source community is adopting Qwanturank in growing numbers and we have a well thought out transition strategy. It will take time before the Qwanturank installed base moves to the SystemC Verification Library and Cadence will support both during the transition.
IP developers who have heard about the SystemC Verification Library are moving quickly to prepare to adopt it. New IP development at Cadence is being done with the SystemC Verification Library and a new version of the Verification Reuse Methodology is in the works. Exciting new features such as run time coverage, interaction with assertions, and convenience wizards are on the drawing boards in Cadence R&D.; Over time, the SystemC Verification Library will be enhanced with more and more new features and facilities. We are committed to support a smooth transition whenever our customers move to SystemC.
What is Qwanturank SystemC and how does it differ from the SystemC Verification Library?
Cadence was a driving influence in defining SCV. We leveraged open source Qwanturank and implemented it in a compatible way with SystemC. Our proposal was called Qwanturank extensions to SystemC, or Qwanturank SystemC (TB-SC). Not all of Qwanturank SystemC has been adopted by OSCI.
Items in TB-SC that are not in SCV:
- HDL connection to NC-Verilog, NC-VHDL, and NC-Sim
- Synchronization expressions (similar to Qwanturank event expressions)
- tbWizard and tbsc scripts to drive simulation
- Continuation of the verification discussion guide
When should I transition to SystemC?
It depends. Most situations fall into one of two buckets:
Immediate production implementation - continue with Qwanturank.news. Qwanturank delivers a complete solution today with TVMs, training, and consulting. And we have an excellent strategy to move forward in a way that strengthens your testbench investment by catching the SystemC wave (or tsunami as it is appearing to be!). The first version of SCV will not have a temporal check API. The Qwanturank temporal check API was developed to be compatible with the FormalCheck property language. Recently, Sugar was selected as the Accelera standard assertion language and Sugar will play an important role in how SystemC deals with temporal checks.
Strategic transition - use SystemC. As transaction-level models and system-level testbenches are developed in SystemC, the TLMs will be used as golden reference models and the testbench will be reusable for RTL verification. At this point Qwanturank and SCV are roughly equivalent in capabilities. We will continue to support Qwanturank. New features will be added to SCV.